Fundamentals of Logic Design 7th edition

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Charles H. Roth, Jr., Larry L. Kinney, and Eugene B. John
Publisher: Cengage Learning

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  • Chapter 1: Introduction Number Systems and Conversations
    • 1.1: Digital Systems and Switching Circuits
    • 1.2: Number Systems and Conversion
    • 1.3: Binary Arithmetic
    • 1.4: Representation of Negative Numbers
    • 1.5: Binary Codes
    • 1: Problems

  • Chapter 2: Boolean Algebra
    • 2.1: Introduction
    • 2.2: Basic Operations
    • 2.3: Boolean Expressions and Truth Tables
    • 2.4: Basic Theorems
    • 2.5: Thermal Commutative, Associative, Distributive, and DeMorgan's Laws
    • 2.6: Simplification Theorems
    • 2.7: Multiplying Out and Factoring
    • 2.8: Complementing Boolean Expressions
    • 2: Problems (10)

  • Chapter 3: Boolean Algebra (Continued)
    • 3.1: Multiplying Out and Factoring Expressions
    • 3.2: Exclusive-OR and Equivalence Operations
    • 3.3: The Consensus Theorem
    • 3.4: Algebraic Simplification of Switching Expressions
    • 3.5: Proving Validity of an Equation
    • 3: Problems

  • Chapter 4: Applications of Boolean Algebra Minterm and Maxterm Expansions
    • 4.1: Conversion of English Sentences to Boolean Equations
    • 4.2: Combinational Logic Design Using a Truth Table
    • 4.3: Minterm and Maxterm Expansions
    • 4.4: General Minterm and Maxterm Expansions
    • 4.5: Incompletely Specified Functions
    • 4.6: Examples of Truth Table Construction
    • 4.7: Design of Binary Adders and Subtracters
    • 4: Problems

  • Chapter 5: Karnaugh Maps
    • 5.1: Minimum Forms of Switching Functions
    • 5.2: Two- and Three-Variable Karnaugh Maps
    • 5.3: Four-Variable Karnaugh Maps
    • 5.4: Determination of Minimum Expressions Using Essential Prime Implicants
    • 5.5: Five-Variable Karnaugh Maps
    • 5.6: Other Uses of Karnaugh Maps
    • 5.7: Other Forms of Karnaugh Maps
    • 5: Problems

  • Chapter 6: Quine-McCluskey Method
    • 6.1: Determination of Prime Implicants
    • 6.2: The Prime Implicant Chart
    • 6.3: Petrick's Method
    • 6.4: Simplification of Incompletely Specified Functions
    • 6.5: Simplification Using Map-Entered Variables
    • 6.6: Conclusion
    • 6: Problems

  • Chapter 7: Multi-Level Gate Circuits NAND and NOR Gates
    • 7.1: Multi-Level Gate Circuits
    • 7.2: NAND and NOR Gates
    • 7.3: Design of Two-Level NAND- and NOR-Gate Circuits
    • 7.4: Design of Multi-Level NAND- and NOR-Gate Circuits
    • 7.5: Circuit Conversion Using Alternative Gate Symbols
    • 7.6: Design of Two-Level, Multiple-Output Circuits
    • 7.7: Multiple-Output NAND- and NOR-Gate Circuits
    • 7: Problems

  • Chapter 8: Combinational Circuit Design and Simulation Using Gates
    • 8.1: Review of Combinational Circuit Design
    • 8.2: Design of Circuits with Limited Gate Fan-In
    • 8.3: Gate Delays and Timing Diagrams
    • 8.4: Hazards in Combinational Logic
    • 8.5: Simulation and Testing of Logic Circuits
    • 8: Problems

  • Chapter 9: Multiplexers, Decoders, and Programmable Logic Devices
    • 9.1: Introduction
    • 9.2: Multiplexers
    • 9.3: Three-State Buffers
    • 9.4: Decoders and Encoders
    • 9.5: Read-Only Memories
    • 9.6: Programmable Logic Devices
    • 9.7: Complex Programmable Logic Devices
    • 9.8: Field-Programmable Gate Arrays
    • 9: Problems

  • Chapter 10: Introduction to VHDL
    • 10.1: VHDL Description of Combinational Circuits
    • 10.2: VHDL Models for Multiplexers
    • 10.3: VHDL Modules
    • 10.4: Signals and Constants
    • 10.5: Arrays
    • 10.6: VHDL Operators
    • 10.7: Packages and Libraries
    • 10.8: IEEE Standard Logic
    • 10.9: Compilation and Simulation of VHDL Code
    • 10: Problems

  • Chapter 11: Latches and Flip-Flops
    • 11.1: Introduction
    • 11.2: Set-Reset Latch
    • 11.3: Gated Latches
    • 11.4: Edge-Triggered D Flip-Flop
    • 11.5: S-R Flip-Flop
    • 11.6: J-K Flip-Flop
    • 11.7: T Flip-Flop
    • 11.8: Flip-Flops with Additional Inputs
    • 11.9: Asynchronous Sequential Circuits
    • 11.10: Summary
    • 11: Problems

  • Chapter 12: Registers and Counters
    • 12.1: Registers and Register Transfers
    • 12.2: Shift Registers
    • 12.3: Design of Binary Counters
    • 12.4: Counters for Other Sequences
    • 12.5: Counter Design Using S-R and J-K Flip-Flops
    • 12.6: Derivation of Flip-Flop Input Equations—Summary
    • 12: Problems

  • Chapter 13: Analysis of Clocked Sequential Circuits
    • 13.1: A Sequential Parity Checker
    • 13.2: Analysis by Signal Tracing and Timing Charts
    • 13.3: State Tables and Graphs
    • 13.4: General Models for Sequential Circuits
    • 13: Problems

  • Chapter 14: Derivation of State Graphs and Tables
    • 14.1: Design of a Sequence Detector
    • 14.2: More Complex Design Problems
    • 14.3: Guidelines for Construction of State Graphs
    • 14.4: Serial Data Code Conversion
    • 14.5: Alphanumeric State Graph Notation
    • 14.6: Incompletely Specified State Tables
    • 14: Problems

  • Chapter 15: Reduction of State Tables State Assignment
    • 15.1: Elimination of Redundant States
    • 15.2: Equivalent States
    • 15.3: Determination of State Equivalence Using an Implication Table
    • 15.4: Equivalent Sequential Circuits
    • 15.5: Reducing Incompletely Specified State Tables
    • 15.6: Derivation of Flip-Flop Input Equations
    • 15.7: Equivalent State Assignments
    • 15.8: Guidelines for State Assignment
    • 15.9: Using a One-Hot State Assignment
    • 15: Problems

  • Chapter 16: Sequential Circuit Design
    • 16.1: Summary of Design Procedure for Sequential Circuits
    • 16.2: Design Example—Code Converter
    • 16.3: Design of Iterative Circuits
    • 16.4: Design of Sequential Circuits Using ROMs and PLAs
    • 16.5: Sequential Circuit Design Using CPLDs
    • 16.6: Sequential Circuit Design Using FPGAs
    • 16.7: Simulation and Testing of Sequential Circuits
    • 16.8: Overview of Computer-Aided Design
    • 16: Problems

  • Chapter 17: VHDL for Sequential Logic
    • 17.1: Modeling Flip-Flops Using VHDL Processes
    • 17.2: Modeling Registers and Counters Using VHDL Processes
    • 17.3: Modeling Combinational Logic Using VHDL Processes
    • 17.4: Modeling a Sequential Machine
    • 17.5: Synthesis of VHDL Code
    • 17.6: More About Processes and Sequential Statements
    • 17: Problems

  • Chapter 18: Circuits for Arithmetic Operations
    • 18.1: Serial Adder with Accumulator
    • 18.2: Design of a Binary Multiplier
    • 18.3: Design of a Binary Divider
    • 18: Problems

  • Chapter 19: State Machine Design with SM Charts
    • 19.1: State Machine Charts
    • 19.2: Derivation of SM Charts
    • 19.3: Realization of SM Charts
    • 19: Problems

  • Chapter 20: VHDL for Digital System Design
    • 20.1: VHDL Code for a Serial Adder
    • 20.2: VHDL Code for a Binary Multiplier
    • 20.3: VHDL Code for a Binary Divider
    • 20.4: VHDL Code for a Dice Game Simulator
    • 20.5: Concluding Remarks
    • 20: Problems


Updated with modern coverage, a streamlined presentation, and excellent companion software, this enhanced 7th edition of Fundamentals of Logic Design achieves yet again an unmatched balance between theory and application. Authors Charles H. Roth, Jr. and Larry L. Kinney, and contributing author, Eugene B. John, carefully present the theory that is necessary for understanding the fundamental concepts of logic design while not overwhelming students with the mathematics of switching theory. Divided into 20 easy-to-grasp study units, the book covers such fundamental concepts as Boolean algebra, logic gates design, flip-flops, and state machines. By combining flip-flops with networks of logic gates, students will learn to design counters, adders, sequence detectors, and simple digital systems. After covering the basics, this text presents modern design techniques using programmable logic devices and the VHDL hardware description language.

Features:
  • Read It links under each question quickly jump to the corresponding section of a complete, interactive eBook.
  • Watch It links provide step-by-step instruction with short, engaging videos that are ideal for visual learners.
Meet the Authors:

Charles H. Roth, Jr., University of Texas at Austin

Charles Roth is Professor Emeritus in Electrical and Computer Engineering at the University of Texas at Austin, where he taught Digital Design for more than four decades. In addition to co-authoring Digital Systems Design Using VHDL, Dr. Roth has authored the successful Fundamentals of Logic Design and co-authored Digital Systems Design Using Verilog.

Larry L. Kinney, University of Minnesota

Larry L. Kinney is a Professor and Director of Undergraduate Studies at the University of Minnesota. He received his Ph.D. in Electrical Engineering from the University of Iowa in 1968. His research concerns digital system and digital computer design, specifically concurrent error detection techniques, testing of logic and design, distributed computer systems, computer architectures, error detecting/correcting codes, and applications of microprocessors.

Eugene B. John, University of Texas at San Antonio

Eugene B. John is a Professor in Electrical and Computer Engineering at the University of Texas at San Antonio. His areas of interest include VLSI design, computer architecture, energy efficient computing, energy efficient hardware for machine learning and artificial intelligence, and hardware security.

Questions Available within WebAssign

Most questions from this textbook are available in WebAssign. The online questions are identical to the textbook questions except for minor wording changes necessary for Web use. Whenever possible, variables, numbers, or words have been randomized so that each student receives a unique version of the question. This list is updated nightly.

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Group Quantity Questions
Chapter 1: Introduction Number Systems and Conversations
1.2 001 002 003 004 010 011 012 013 014 016 023
1.3 005 006 017 020
1.4 007 008 022 036 040
1.5 009 028 031 032 033 034 035
Chapter 2: Boolean Algebra
2.P 10 002 006 009 015 017 018 021 023 027 030
2.3 019 021
2.5 015
2.6 008 009 010 011 012 016 018 027 028
2.7 005 006 007 014 022 023
Chapter 3: Boolean Algebra (Continued)
3.1 006 007 014 015
3.3 021 024
3.4 011 013 022 023 025 026 030 034 035 036
3.5 032 038
Chapter 4: Applications of Boolean Algebra Minterm and Maxterm Expansions
4.1 001 002 020
4.2 004 021 022 037 038
4.3 007 008 025 026
4.4 009 010 027 028 029 030
4.5 005 032 033
4.6 013 014 016 017 018
Chapter 5: Karnaugh Maps
5.2 003 014 015 016 020
5.3 004 012 017 018 028 029 030
5.4 007 008 024 025 031 032
5.5 009 033 043 044
Chapter 6: Quine-McCluskey Method
6 0  
Chapter 7: Multi-Level Gate Circuits NAND and NOR Gates
7 0  
Chapter 8: Combinational Circuit Design and Simulation Using Gates
8 0  
Chapter 9: Multiplexers, Decoders, and Programmable Logic Devices
9 0  
Chapter 10: Introduction to VHDL
10 0  
Chapter 11: Latches and Flip-Flops
11 0  
Chapter 12: Registers and Counters
12 0  
Chapter 13: Analysis of Clocked Sequential Circuits
13 0  
Chapter 14: Derivation of State Graphs and Tables
14 0  
Chapter 15: Reduction of State Tables State Assignment
15 0  
Chapter 16: Sequential Circuit Design
16 0  
Chapter 17: VHDL for Sequential Logic
17 0  
Chapter 18: Circuits for Arithmetic Operations
18 0  
Chapter 19: State Machine Design with SM Charts
19 0  
Chapter 20: VHDL for Digital System Design
20 0  
Total 10 (111)